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InP DHBT-based clock and data recovery circuits for ultra-high-speed optical data links

dc.contributor.authorMakon, Robert Elvis*
dc.date.accessioned2021-02-11T16:18:34Z
dc.date.available2021-02-11T16:18:34Z
dc.date.issued2006*
dc.date.submitted2019-07-30 20:01:58*
dc.identifier34682*
dc.identifier.urihttps://directory.doabooks.org/handle/20.500.12854/50310
dc.description.abstractIn this work, up to 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuits with 1:2 demultiplexer are developed. The integrated circuits are manufactured using an InP double heterojunction bipolar transistor (DHBT) technology, featuring cut-off frequency values of more than 250 GHz. The outstanding and (to some extent) record achievements throughout the work make an essential contribution to the development of future optical telecommunication networks operating at 80 Gbit/s.*
dc.languageEnglish*
dc.subjectT1-995*
dc.subject.classificationthema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TB Technology: general issuesen_US
dc.subject.otherInP DHBT*
dc.subject.otherPhase detector*
dc.subject.otherPhase-locked loop*
dc.subject.otherOptical link*
dc.subject.otherClock and data recovery*
dc.titleInP DHBT-based clock and data recovery circuits for ultra-high-speed optical data links*
dc.typebook
oapen.identifier.doi10.5445/KSP/1000004568*
oapen.relation.isPublishedBy68fffc18-8f7b-44fa-ac7e-0b7d7d979bd2*
oapen.relation.isbn3866440456*
oapen.pagesVI, 167 p.*
peerreview.review.typeFull text
peerreview.anonymityAll identities known
peerreview.reviewer.typeInternal editor
peerreview.reviewer.typeExternal peer reviewer
peerreview.review.stagePre-publication
peerreview.open.reviewNo
peerreview.publish.responsibilityScientific or Editorial Board
peerreview.id8ad5c235-9810-49eb-b358-27c8675324d9
peerreview.titleDissertations (Dissertationen)


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